 |
Biologically-inspired hardware for sophisticated imaging tasks |
|
|
|
|
|
|
|
|
|
| Company | Products | Technology | Projects | Demos | Home | ||
| Management | Customers | Services | Brochure | Careers | Contact Us |
Technology: Analog Image Processing Arrays
CSC designed Analog Image Processing (AIP) arrays are versatile spatio-temporal filtering ASICs under on-chip digital control.
| Analog Image Processing Arrays | |
 |
| Accepting serial video input from an FPA ROIC or other device, or operating as a complete sensor/processor performing signal detection through per-pixel connectivity to a bumped FPA, CSC's AIP arrays provide a highly programmable filtering device that can be used singly or in multi-chip architectures. Spatial and temporal filtering operations are implemented using programmable switched capacitor pixel interconnections that comprise a resistive grid network after Caver Mead. Operated as a FPA/ROIC, the processors can embody a compact sensor/processor camera-on-a-chip by accepting per-pixel detector current directly from an attached FPA into detection circuitry in the processing array and efficiently perform spatial and temporal filtering of the array data while maintaining the two-dimensional data format. | |
|
|
||
|
||
 |
||
|
||
| Performing computationally intensive spatial domain isotropic and oriented anisotropic convolutions in analog allows the processors to perform full image array spatial filtering at high video rates while consuming little power. This technology is enabling to flight and man portable surveillance systems requiring spatiotemporal filtering operations that parallel mammalian early vision processing for scene understanding at high frame rates.
For infrared sensing from lightweight low lift and low power capable flight surveillance platforms the on-chip processing can be used to implement detector nonuniformity correction (NUC) at video rates and therefore obviate the need for electronic shuttering and/or digital post-ROIC processing that typically results in a heavier more power hungry camera. | ||
|
||
|
||
| CSCs next generation AIP aggregate the processing capability of five of the previous generation ASICs with extensive programmable on-chip signal combining. Different modes of operation allow multiple selectable lowpass, bandpass and highpass spatial and temporal filters to be produced and combined to effect parallel and cascaded combinations. Spatial phase filtering can also be implemented to allow oriented gradient Difference of Gaussian filtering as well as producing scene Motion Energy output according to Adelson & Bergen. | |
|
 |
||
All material ©2000-2007 by Computational Sensors Corporation
Terms of use
